1. Field of the Invention
The present invention relates generally to the field of digital camera systems, and specifically, to a single-instruction multiple data digital camera system that integrates on-chip sensing and parallel processing.
2. Background Information
Sensor arrays that discretely sample images are becoming increasingly popular in digital cameras and camcorders. A complementary metal-oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) sensor array typically includes an array of pixel sensors that discretely sample an image. The output of each pixel sensor is fed to an on-chip analog-to-digital converter which receives the analog samples and converts them into a digital bit stream. The digital bit stream is routed off-chip to a host system which operates on the data, as required by a particular application. For example, the digital bit stream that makes up an image may be manipulated for enhancing the image or may be compressed and stored in memory.
However, this type of digital camera system has several drawbacks. First, the digital bit stream coming off-chip demands a high bandwidth communication channel, requiring a high bandwidth, external device to receive the digital bit stream. Second, the host processor is burdened with performing a considerable amount of processing such as image filtering, compression, etc., which reduces the bandwidth of the host processor for performing other tasks. Moreover, storage requirements for portable digital cameras become prohibitive.
A single-chip digital camera system is described. In one embodiment, the single-chip digital camera system comprises a sensor array including rows and columns of discrete sensor elements, corresponding analog-to-digital converters to convert analog values into digital data, a storage element coupled to the analog-to-digital converters, to store the digital data, and a plurality of arithmetic logic units coupled to the storage element, to operate on the digital data.